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| Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5565 Rev. 2.0, 11/2008 MPC5565 Microcontroller Data Sheet by: Microcontroller Division This document provides electrical specifications, pin assignments, and package diagrams for the MPC5565 microcontroller device. For functional characteristics, refer to the MPC5565 Microcontroller Reference Manual. Contents 1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 5 3.3 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 EMI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VRC and POR Electrical Specifications . . . . . . . . . 9 3.7 Power-Up/Down Sequencing. . . . . . . . . . . . . . . . . 10 3.8 DC Electrical Specifications . . . . . . . . . . . . . . . . . 13 3.9 Oscillator and FMPLL Electrical Characteristics . . 20 3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22 3.11 H7Fa Flash Memory Electrical Characteristics . . . 23 3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.1 MPC5565 324 PBGA Pinouts . . . . . . . . . . . . . . . . 46 4.2 MPC5565 324-Pin Package Dimensions. . . . . . . . 47 Revision History for the MPC5565 Data Sheet . . . . . . . 49 5.1 Changes to Revision 1.0 in Revision 2.0 . . . . . . . . 49 5.2 Changes to Revision 0.0 in Revision 1.0 . . . . . . . . 52 1 Overview The MPC5565 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the Power ArchitectureTM embedded technology. This family of parts has many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family. The host processor core of this device complies with the Power Architecture embedded category that is 100% user-mode compatible (including floating point library) with the original Power PCTM user instruction set architecture (UISA). The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. 4 5 (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The host processor core of the MPC5565 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to significantly reduce the code size footprint. The MPC5565 has two levels of memory hierarchy. The fastest accesses are to the 8-kilobytes (KB) unified cache. The next level in the hierarchy contains the 80-KB on-chip internal SRAM and two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data. The external bus interface is designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5565 are performed by an enhanced time processor unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language. The less complex timer functions of the MPC5565 are performed by the enhanced modular input/output system (eMIOS). The eMIOS' 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIOs) signals. The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 324 package has 40-channels. The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. MPC5565 Microcontroller Data Sheet, Rev. 2.0 2 Freescale Semiconductor Ordering Information 2 Ordering Information M PC 5565 M ZQ 80 R Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status Operating Frequency 80 = 80 MHz 112 = 112 MHz 132 = 132 MHz Tape and Reel Status R = Tape and reel (blank) = Trays Qualification Status P = Pre qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Temperature Range M = -40 C to 125 C Package Identifier ZQ = 324PBGA SnPb VZ = 324PBGA Pb-free Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5500 Family Part Number Example Unless noted in this data sheet, all specifications apply from TL to TH. Table 1. Orderable Part Numbers Freescale Part MPC5565MVZ132 MPC5565MVZ112 MPC5565MVZ80 MPC5565MZQ132 MPC5565MZQ112 MPC5565MZQ80 1 Number1 Speed (MHz) Package Description Nominal 132 MPC5565 324 package Lead-free (PbFree) 112 80 132 MPC5565 324 package Leaded (SnPb) 112 80 Max. 3 (fMAX) 135 114 82 135 114 82 Operating Temperature 2 Min. (TL) Max. (TH) -40 C 125 C -40 C 125 C All devices are PPC5565, rather than MPC5565 or SPC5565, until product qualifications are complete. Not all configurations are available in the PPC parts. 2 The lowest ambient operating temperature is referenced by T ; the highest ambient operating temperature is referenced by T . L H 3 Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 3 Electrical Characteristics 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Spec 1 2 4 5 6 7 8 9 10 11 12 Maximum Ratings Table 2. Absolute Maximum Ratings 1 Characteristic 1.5 V core supply voltage 2 Flash program/erase voltage Flash read voltage SRAM standby voltage Clock synthesizer voltage 3.3 V I/O buffer voltage Voltage regulator control input voltage Analog supply voltage (reference to VSSA) I/O supply voltage (fast I/O pads) 4 3 3 Symbol VDD VPP VFLASH VSTBY VDDSYN VDD33 VRC33 VDDA VDDE VDDEH VIN Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1.0 5 -1.0 5 -0.3 -0.1 -VDDA -0.3 -5.5 -0.3 -VDDA -0.3 Max. 1.7 6.5 4.6 1.7 4.6 4.6 4.6 5.5 4.6 6.5 6.5 6 4.6 7 5.5 0.1 VDD 5.5 5.5 0.3 VDDEH 0.3 Unit V V V V V V V V V V V V V V V V V V V I/O supply voltage (slow and medium I/O pads) DC input voltage VDDEH powered I/O pads VDDE powered I/O pads 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Analog reference high voltage (reference to VRL) VSS to VSSA differential voltage VDD to VDDA differential voltage VREF differential voltage VRH to VDDA differential voltage VRL to VSSA differential voltage VDDEH to VDDA differential voltage VDDF to VDD differential voltage VSSSYN to VSS differential voltage VRCVSS to VSS differential voltage Maximum DC digital input current 8 (per pin, applies to all digital pins) 4 Maximum DC analog input current 9 (per pin, applies to all analog pins) Maximum operating temperature range 10 Die junction temperature Storage temperature range VRH VSS - VSSA VDD - VDDA VRH - VRL VRH - VDDA VRL - VSSA VDDEH - VDDA VDDF - VDD VSSSYN - VSS VRCVSS - VSS IMAXD IMAXA TJ TSTG VRC33 to VDDSYN differential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a. -0.1 -0.1 -2 -3 TL -55.0 0.1 0.1 2 3 150.0 150.0 V V mA mA oC oC MPC5565 Microcontroller Data Sheet, Rev. 2.0 4 Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings 1 (continued) Spec 28 Characteristic Maximum solder temperature 11 Lead free (Pb-free) Leaded (SnPb) Moisture sensitivity level 12 Symbol TSDR MSL Min. -- -- -- Max. 260.0 245.0 3 Unit o C 29 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability or cause permanent damage to the device. 2 1.5 V 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC. 3 All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH. 4 AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 5 Internal structures hold the voltage greater than -1.0 V if the injection current limit of 2 mA is met. Keep the negative DC voltage greater than -0.6 V on SINB during the internal power-on reset (POR) state. 6 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 7 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 8 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 9 Total injection current for all analog input pins must not exceed 15 mA. 10 Lifetime operation at these specification limits is not guaranteed. 11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D. 12 Moisture sensitivity per JEDEC test method A112. 3.2 Thermal Characteristics Table 3. MPC5565 Thermal Characteristics The shaded rows in the following table indicate information specific to a four-layer board. Spec 1 2 3 4 5 6 7 1 MPC5565 Thermal Characteristic Junction to ambient Junction to ambient 1, 2, 1, 3, Symbol RJA RJA RJMA RJMA RJB RJC JT 324 PBGA 29 19 23 16 10 7 2 Unit C/W C/W C/W C/W C/W C/W C/W natural convection (one-layer board) natural convection (four-layer board 2s2p) Junction to ambient (@200 ft./min., one-layer board) Junction to ambient (@200 ft./min., four-layer board 2s2p) Junction to board Junction to case 5 6 4 (four-layer board 2s2p) Junction to package top , natural convection 2 3 4 5 6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 5 Electrical Characteristics 3.2.1 General Notes for Specifications at Maximum Junction Temperature An estimation of the device junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: * Construction of the application board (number of planes) * Effective size of the board which cools the component * Quality of the thermal and electrical connections to the planes * Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: * One oz. (35 micron nominal thickness) internal planes * Components are well separated * Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. MPC5565 Microcontroller Data Sheet, Rev. 2.0 6 Freescale Semiconductor Electrical Characteristics At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction-to-board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (oC/W) RJC = junction-to-case thermal resistance (oC/W) RCA = case-to-ambient thermal resistance (oC/W) RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 7 Electrical Characteristics The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 3081 Zanker Rd. San Jose, CA., 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the web at http://www.jedec.org. 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. 3. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 3.3 Package The MPC5565 is available in packaged form. Read the package options in Section 2, "Ordering Information." Refer to Section 4, "Mechanicals," for pinouts and package drawings. 3.4 Spec 1 2 3 4 5 6 7 1 EMI (Electromagnetic Interference) Characteristics Table 4. EMI Testing Specifications 1 Characteristic Scan range Operating frequency VDD operating voltages VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages VPP, VDDEH, VDDA operating voltages Maximum amplitude Operating temperature Minimum 0.15 -- -- -- -- -- -- Typical -- -- 1.5 3.3 5.0 -- -- Maximum 1000 fMAX -- -- -- 14 32 3 25 2 Unit MHz MHz V V V dBuV oC EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554 and applied to the MPC5500 family as generic EMI performance data. 2 Measured with the single-chip EMI program. 3 Measured with the expanded EMI program. MPC5565 Microcontroller Data Sheet, Rev. 2.0 8 Freescale Semiconductor Electrical Characteristics 3.5 ESD (Electromagnetic Static Discharge) Characteristics Table 5. ESD Ratings 1, 2 Characteristic Symbol Value 2000 R1 C 1500 100 500 (all pins) 750 (corner pins) -- -- -- 1 1 1 V Unit V pF ESD for human body model (HBM) HBM circuit description ESD for field induced charge model (FDCM) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) Interval of pulses 1 2 -- -- second All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. Device failure is defined as: `If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature. 3.6 Voltage Regulator Controller (VRC) and Power-On Reset (POR) Electrical Specifications Table 6. VRC and POR Electrical Specifications The following table lists the VRC and POR electrical specifications: Spec 1 1.5 V (VDD) POR 1 Characteristic Negated (ramp up) Asserted (ramp down) 1 Symbol VPOR15 Min. 1.1 1.1 0.0 2.0 2.0 0.0 2.0 2.0 1.0 2.0 Max. 1.35 1.35 0.30 2.85 2.85 0.30 2.85 2.85 2.0 2.85 Units V 2 3.3 V (VDDSYN) POR Asserted (ramp up) Negated (ramp up) Asserted (ramp down) Negated (ramp down) Negated (ramp up) Asserted (ramp down) Before VRC allows the pass transistor to start turning on VPOR33 V 3 4 5 RESET pin supply (VDDEH6) POR 1, 2 VPOR5 VTRANS_START VTRANS_ON VVRC33REG V V V VRC33 voltage When VRC allows the pass transistor to completely turn on 3, 4 When the voltage is greater than the voltage at which the VRC keeps the 1.5 V supply in regulation 5, 6 6 Current can be sourced 7 by VRCCTL at Tj: 3.0 11.0 -- -- -- -- 1.0 V mA mA mA V - 40o C 25 C 150o C VDD33_LAG o IVRCCTL 7 9.0 7.5 -- 8 Voltage differential during power up such that: VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach the VPOR33 and VPOR5 minimums respectively. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 9 Electrical Characteristics Table 6. VRC and POR Electrical Specifications (continued) Spec 9 Characteristic Absolute value of slew rate on power supply pins Required gain at Tj: - 40 C IDD / IVRCCTL (@ fsys = fMAX) 6, 7, 8, 9 25o C 150 C 1 o o Symbol -- 10 Min. -- 40 Max. 50 -- -- 500 Units V/ms -- -- -- 10 BETA 45 55 The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts. 2 VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5. 3 Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range. 4 It is possible to reach the current limit during ramp up--do not treat this event as short circuit current. 5 At peak current for device. 6 Requires compliance with Freescale's recommended board requirements and transistor recommendations. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance (less than 1 ). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal) bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals. 7I VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V. 8 Refer to Table 1 for the maximum operating frequency. 9 Values are based on I DD from high-use applications as explained in the IDD Electrical Specification. 10 BETA is the worst-case external transistor BETA. It is measured on a per-part basis and calculated as (I DD / IVRCCTL). 3.7 Power-Up/Down Sequencing Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing, VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is not used. Refer to Section 3.7.2, "Power-Up Sequence (VRC33 Grounded)," and Section 3.7.3, "Power-Down Sequence (VRC33 Grounded)." Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33." Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. MPC5565 Microcontroller Data Sheet, Rev. 2.0 10 Freescale Semiconductor Electrical Characteristics When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification. There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending on which supplies are powered. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type). Table 7. Pin Status for Fast Pads During the Power Sequence VDDE Low VDDE VDDE VDDE VDDE VDDE VDD33 -- Low Low VDD33 VDD33 VDD33 VDD -- Low VDD Low VDD VDD POR Asserted Asserted Asserted Asserted Asserted Negated Pin Status for Fast Pad Output Driver pad_fc (fast) Low High High High impedance (Hi-Z) Hi-Z Functional Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and pad_sh (slow type). Table 8. Pin Status for Medium and Slow Pads During the Power Sequence VDDEH Low VDDEH VDDEH VDDEH VDD -- Low VDD VDD POR Asserted Asserted Asserted Negated Pin Status for Medium and Slow Pad Output Driver pad_mh (medium) pad_sh (slow) Low High impedance (Hi-Z) Hi-Z Functional The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins during power up. Before exiting the internal POR state, the pins go to a high-impedance state until POR negates. When the internal POR negates, the functional state of the signal during reset applies and the weak-pull devices (up or down) are enabled as defined in the device reference manual. If VDD is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH. To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to enable the external circuitry connected to the device outputs. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 11 Electrical Characteristics 3.7.1 Input Value of Pins During POR Dependent on VDD33 When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification applies during power up only. VDD33 has no lead or lag requirements when powering down. 3.7.2 Power-Up Sequence (VRC33 Grounded) The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET POR negate. VDDSYN and RESET Power VDD 2.0 V 1.35 V VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V Figure 2. Power-Up Sequence (VRC33 Grounded) 3.7.3 Power-Down Sequence (VRC33 Grounded) The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See Table 6, footnote 1. MPC5565 Microcontroller Data Sheet, Rev. 2.0 12 Freescale Semiconductor Electrical Characteristics 3.8 DC Electrical Specifications Table 9. DC Electrical Specifications (TA = TL to TH) Spec 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 Characteristic Core supply voltage (average DC RMS voltage) Input/output supply voltage (fast input/output) 1 Symbol VDD VDDE VDDEH VDD33 VRC33 VDDA VPP VFLASH VSTBY VDDSYN VIH_F VIL_F VIH_S VIL_S VHYS_F VHYS_S VINDC VOH_F VOH_S VOL_F VOL_S Min 1.35 1.62 3.0 3.0 3.0 4.5 4.5 3.0 0.8 3.0 0.65 x VDDE VSS - 0.3 0.65 x VDDEH VSS - 0.3 Max. 1.65 3.6 5.25 3.6 3.6 5.25 5.25 3.6 1.2 3.6 VDDE + 0.3 0.35 x VDDE VDDEH + 0.3 0.35 x VDDEH Unit V V V V V V V V V V V V V V V V V V V V V Input/output supply voltage (slow and medium input/output) 3.3 V input/output buffer voltage Voltage regulator control input voltage Analog supply voltage 2 Flash programming voltage 3 Flash read voltage SRAM standby voltage 4 Clock synthesizer operating voltage Fast I/O input high voltage Fast I/O input low voltage Medium and slow I/O input high voltage Medium and slow I/O input low voltage Fast input hysteresis Medium and slow I/O input hysteresis Analog input voltage Fast output high voltage ( IOH_F = -2.0 mA ) Slow and medium output high voltage IOH_S = -2.0 mA IOH_S = -1.0 mA Fast output low voltage ( IOL_F = 2.0 mA ) Slow and medium output low voltage IOL_S = 2.0 mA IOL_S = 1.0 mA Load capacitance (fast I/O) 5 DSC (SIU_PCR[8:9] ) = 0b00 = 0b01 = 0b10 = 0b11 Input capacitance (digital pins) Input capacitance (analog pins) Input capacitance: (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) 0.1 x VDDE 0.1 x VDDEH VSSA - 0.3 0.8 x VDDE 0.80 x VDDEH 0.85 x VDDEH -- -- 0.20 x VDDEH 0.15 x VDDEH -- -- -- -- -- -- -- 10 20 30 50 7 10 12 VDDA + 0.3 -- -- 0.2 x VDDE 21 22 23 CL pF pF pF pF pF pF pF 24 25 26 CIN CIN_A CIN_M MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 13 Electrical Characteristics Table 9. DC Electrical Specifications (TA = TL to TH) (continued) Spec Characteristic Symbol Min Max. Unit 27a Operating current 1.5 V supplies @ 135 MHz: 6 VDD (including VDDF max current) @1.65 V typical use 7, 8 VDD (including VDDF max current) @1.35 V typical use 7, 8 VDD (including VDDF max current) @1.65 V high use 8, 9 VDD (including VDDF max current) @1.35 V high use 8, 9 27b Operating current 1.5 V supplies @ 114 MHz: 6 VDD (including VDDF max current)@1.65 V typical use 7, 8 VDD (including VDDF max current) @1.35 V typical use 7, 8 VDD (including VDDF max current) @1.65 V high use 8, 9 VDD (including VDDF max current) @1.35 V high use 8, 9 27c Operating current 1.5 V supplies @ 82 MHz: 6 VDD (including VDDF max current) @1.65 V typical use 7, 8 VDD (including VDDF max current) @1.35 V typical use 7, 8 VDD (including VDDF max current) @1.65 V high use 8, 9 VDD (including VDDF max current) @1.35 V high use 8, 9 27d Refer to Figure 3 for an interpolation of this data.11 IDD_STBY @ 25o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDD_STBY @ 60o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDD_STBY @ 150o C (Tj) VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V 28 Operating current 3.3 V supplies @ fMAX MHz VDD33 12 IDD_33 -- 2 + (values derived from procedure of footnote 12) 10 15 20.0 1.0 25.0 mA IDD IDD IDD IDD -- -- -- -- 33010 22510 38510 29010 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 41010 31010 46010 37010 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 46010 36010 51010 41010 mA mA mA mA IDD_STBY IDD_STBY IDD_STBY -- -- -- 20 30 50 A A A A A A A A A IDD_STBY IDD_STBY IDD_STBY -- -- -- 70 100 200 IDD_STBY IDD_STBY IDD_STBY -- -- -- 1200 1500 2000 VFLASH VDDSYN 29 Operating current 5.0 V supplies (12 MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog reference supply current (VRH, VRL) VPP IVFLASH IDDSYN IDD_A IREF IPP -- -- -- -- -- mA mA mA mA mA MPC5565 Microcontroller Data Sheet, Rev. 2.0 14 Freescale Semiconductor Electrical Characteristics Table 9. DC Electrical Specifications (TA = TL to TH) (continued) Spec 30 Characteristic Operating current VDDE supplies: 13 VDDEH1 VDDE2 VDDE3 VDDEH4 VDDE5 VDDEH6 VDDE7 VDDEH8 VDDEH9 Fast I/O weak pullup current 14 1.62-1.98 V 2.25-2.75 V 3.00-3.60 V Fast I/O weak pulldown current 14 1.62-1.98 V 2.25-2.75 V 3.00-3.60 V 32 Slow and medium I/O weak pullup/down current 14 3.0-3.6 V 4.5-5.5 V I/O input leakage current 15 DC injection current (per pin) Analog input current, channel off 16 Symbol Min Max. Unit IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 -- -- -- -- -- -- -- -- -- 10 20 20 Refer to Footnote 13 mA mA mA mA mA mA mA mA mA A A A A A A A A A mA nA A mV V mV V V mV mV mV V V C 31 110 130 170 100 130 170 150 170 2.5 2.0 150 2.5 100 VSSA + 0.1 100 VDDA + 0.1 5.25 50 50 100 0.1 18 2.5 TH 50 IACT_F 10 20 20 IACT_S IINACT_D IIC IINACT_A IINACT_AD VSS - VSSA VRL VRL - VSSA VRH VRH - VRL VSSSYN - VSS VRCVSS - VSS VDDF - VDD VRC33 - VDDSYN VIDIFF TA = (TL to TH) -- 10 20 -2.5 -2.0 -150 -2.5 -100 VSSA - 0.1 -100 VDDA - 0.1 4.5 -50 -50 -100 -0.1 -2.5 TL -- 33 34 35 35a Analog input current, shared analog / digital pins (AN[12], AN[13], AN[14], AN[15]) 36 37 38 39 40 41 42 43 VSS to VSSA differential voltage 17 Analog reference low voltage VRL differential voltage Analog reference high voltage VREF differential voltage VSSSYN to VSS differential voltage VRCVSS to VSS differential voltage VDDF to VDD differential voltage 43a VRC33 to VDDSYN differential voltage 44 45 46 1 Analog input differential signal range (with common mode 2.5 V) Operating temperature range, ambient (packaged) Slew rate on power-supply pins V/ms VDDE2 and VDDE3 are limited to 2.25-3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and VDDE3 have a range of 1.6-3.6 V if SIU_ECCR[EBTS] = 1. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 15 Electrical Characteristics 2 3 | VDDA0 - VDDA1 | must be < 0.1 V. VPP can drop to 3.0 V during read operations. 4 If standby operation is not required, connect VSTBY to ground. 5 Applies to CLKOUT, external bus pins, and Nexus pins. 6 Maximum average RMS DC current. 7 Average current measured on automotive benchmark. 8 Peak currents can be higher on specialized code. 9 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents can occur if an "idle" loop that crosses cache lines is run from cache. Design and write code to avoid this condition. 10 Final values listed in specs 27a -27c are based on characterization. 11 Figure 3 shows an illustration of the IDD_STBY values interpolated for these temperature values. 12 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation. 13 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 14 Absolute value of current, measured at V and V . IL IH 15 Weak pullup/down inactive. Measured at V DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. 16 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae. 17 V SSA refers to both VSSA0 and VSSA1. | VSSA0 - VSSA1 | must be < 0.1 V. 18 Up to 0.6 V during power up and power down. MPC5565 Microcontroller Data Sheet, Rev. 2.0 16 Freescale Semiconductor Electrical Characteristics Figure 3 shows an approximate interpolation of the ISTBY worst-case specification to estimate values at different voltages and temperatures. The vertical lines shown at 25 C, 60 C, and 150 C in Figure 3 are the actual IDD_STBY specifications (27d) listed in Table 9. Istby vs. Junction Tem p 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 uA 1000 900 800 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Tem p (C) 0.8V 1.0V 1.2V A Figure 3. ISTBY Worst-case Specifications MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 17 Electrical Characteristics 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. Table 10. I/O Pad Average DC Current (TA = TL to TH)1 Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 Pad Type Symbol Frequency (MHz) 25 Load2 (pF) 50 50 50 200 50 50 50 200 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 Voltage (V) 5.25 5.25 5.25 5.25 5.25 5.25 5.25 5.25 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 Drive Select / Slew Rate Control Setting 11 01 00 00 11 01 00 00 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Current (mA) 8.0 3.2 0.7 2.4 17.3 6.5 1.1 3.9 2.8 5.2 8.5 11.0 1.6 2.9 4.2 6.7 2.4 4.4 7.2 9.3 1.3 2.5 3.5 5.7 1.7 3.1 5.1 6.6 1.0 1.8 2.5 4.0 Slow IDRV_SH 10 2 2 50 20 3.33 3.33 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 Medium IDRV_MH Fast IDRV_FC These values are estimates from simulation and are not tested. Currents apply to output pins only. 2 All loads are lumped. MPC5565 Microcontroller Data Sheet, Rev. 2.0 18 Freescale Semiconductor Electrical Characteristics 3.8.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. VDD33 Pad Average DC Current (TA = TL to TH) 1 Spec Pad Type Symbol Frequency (MHz) Load 2 (pF) Inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 VDD33 (V) VDDE (V) Drive Select Current (mA) Slow Medium I33_SH I33_MH 66 66 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 0.5 0.5 Outputs 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 5.5 5.5 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 NA NA 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0.003 0.003 0.35 0.53 0.62 0.79 0.35 0.44 0.53 0.70 0.30 0.45 0.52 0.67 0.30 0.37 0.45 0.60 0.21 0.31 0.37 0.48 0.21 0.27 0.32 0.42 Fast I33_FC These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 19 Electrical Characteristics 3.9 Oscillator and FMPLL Electrical Characteristics Table 12. FMPLL Electrical Specifications (VDDSYN = 3.0-3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic PLL reference frequency range: 1 Crystal reference2 External reference2 Dual controller (1:1 mode) System frequency 3 System clock period Loss of reference frequency 5 Self-clocked mode (SCM) frequency 6 EXTAL input high voltage crystal mode 7 Symbol Minimum Maximum Unit 1 fref_crystal fref_ext fref_1:1 fsys tCYC fLOR fSCM VIHEXT 8 8 24 fICO(MIN) / 2RFD -- 100 7.4 VXTAL + 0.4 V (VDDE5 / 2) + 0.4 V -- 20 20 fsys / 2 fMAX 4 1 / fsys 1000 17.5 -- MHz 2 3 4 5 MHz ns kHz MHz V 6 All other modes [dual controller (1:1), bypass, external reference] EXTAL input low voltage crystal mode 8 VIHEXT VILEXT -- VXTAL - 0.4 V (VDDE5 / 2) - 0.4 V 6 1.5 1.5 Refer to crystal specification (2 x CL) - CS_EXTAL - CPCB_EXTAL 10 (2 x CL) - CS_XTAL - CPCB_XTAL 10 750 2 V V 7 All other modes [dual controller (1:1), bypass, external reference] XTAL current 9 Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL Crystal manufacturer's recommended capacitive load Discrete load capacitance to connect to EXTAL VILEXT IXTAL CS_XTAL CS_EXTAL CL CL_EXTAL CL_XTAL tlpll tskew tDC fUL fLCK -- 2 -- -- Refer to crystal specification -- V mA pF pF pF 8 9 10 11 12 pF 13 14 15 16 17 18 Discrete load capacitance to connect to XTAL PLL lock time 11 Dual controller (1:1) clock skew (between CLKOUT and EXTAL) 12, 13 Duty cycle of reference Frequency unLOCK range Frequency LOCK range -- -- -2 pF s ns 40 -4.0 -2.0 60 4.0 2.0 % % fSYS % fSYS MPC5565 Microcontroller Data Sheet, Rev. 2.0 20 Freescale Semiconductor Electrical Characteristics Table 12. FMPLL Electrical Specifications (continued) (VDDSYN = 3.0-3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic CLKOUT period jitter, measured at fSYS max: 14, 15 Peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over a 2 ms interval) Frequency modulation range limit 16 (do not exceed fsys maximum) ICO frequency fico = [ fref_crystal x (MFD + 4) ] / (PREDIV + 1) 17 fico = [ fref_ext x (MFD + 4) ] / (PREDIV + 1) Predivider output frequency (to PLL) Symbol CJITTER -- -- CMOD 0.8 5.0 0.01 2.4 Minimum Maximum Unit % fCLKOUT %fSYS 19 20 21 fico fPREDIV 48 fMAX 20 18 MHz 22 1 4 MHz Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time. The designer must thoroughly understand the drift margin of the source clock. 2 The 8-20 MHz crystal or external reference values have PLLCFG[2] pulled low. PLLCFG[2] is not supported pulled high. 3 All internal registers retain data at 0 Hz. 4 Up to the maximum frequency rating of the device (refer to Table 1). 5 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked mode. 6 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f LOR. SCM frequency is measured on the CLKOUT ball with the divider set to divide-by-two of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 7 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vextal - Vxtal) must be 400 mV for the oscillator's comparator to produce the output clock. 8 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vxtal - Vextal) must be 400 mV for the oscillator's comparator to produce the output clock. 9I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 10 C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 11 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal startup time. 12 PLL is operating in 1:1 PLL mode. 13 V DDE = 3.0-3.6 V. 14 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider is set to divide-by-two. 15 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 16 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value. 17 f RFD). sys = fico / (2 18 Maximum value for dual controller (1:1) mode is (fMAX / 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001). MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 21 Electrical Characteristics 3.10 Spec 1 2 3 4 5 6 7 8 9 10 11 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications (TA = TL to TH) Characteristic ADC clock (ADCLK) frequency 1 Conversion cycles Differential Single ended Stop mode recovery time 2 Resolution 3 Symbol FADCLK CC Minimum 1 13 + 2 (15) 14 + 2 (16) Maximum 12 13 + 128 (141) 14 + 128 (142) -- -- 4 8 34 6 4 8 4 5 6 Unit MHz ADCLK cycles s mV Counts 3 Counts Counts Counts Counts Counts mA TSR -- INL6 INL12 DNL6 DNL12 OFFWC GAINWC IINJ EINJ 7, 8, 9, 10 10 1.25 -4 -8 -3 4 INL: 6 MHz ADC clock INL: 12 MHz ADC clock DNL: 6 MHz ADC clock DNL: 12 MHz ADC clock Offset error with calibration Full-scale gain error with calibration Disruptive input injection current -6 4 -4 5 -8 6 -1 1 12 Incremental error due to injection current. All channels are 10 k < Rs <100 k Channel under test has Rs = 10 k, IINJ = IINJMAX, IINJMIN Total unadjusted error (TUE) for single ended conversions with calibration 11, 12, 13, 14, 15 -4 4 Counts 13 1 TUE -4 4 Counts Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a maximum 16 factor. 2 Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform conversions. 3 At V RH - VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count. 4 Guaranteed 10-bit mono tonicity. 5 The absolute value of the offset error without calibration 100 counts. 6 The absolute value of the full scale gain error without calibration 120 counts. 7 Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than VRH, and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 8 Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = - 0.3 V, then use the larger of the calculated values. 10 This condition applies to two adjacent pads on the internal pad. 11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors. 12 TUE does not apply to differential conversions. 13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: -16 counts < TUE < 16 counts. 14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref). 15 Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15]. MPC5565 Microcontroller Data Sheet, Rev. 2.0 22 Freescale Semiconductor Electrical Characteristics 3.11 Spec 3 4 7 9 10 8 11 1 2 3 4 5 6 H7Fa Flash Memory Electrical Characteristics Table 14. Flash Program and Erase Specifications (TA = TL to TH) Flash Program Characteristic Doubleword (64 bits) program time 4 Page program time 4 Symbol Tdwprogram Tpprogram T16kpperase T48kpperase T64kpperase T128kpperase -- Min. -- -- -- -- -- -- 25 Typical 1 10 22 265 345 415 500 -- Initial Max. 2 -- 44 5 Max. 3 500 500 5000 5000 5000 7500 -- Unit s s ms ms ms ms MHz 16 KB block pre-program and erase time 48 KB block pre-program and erase time 64 KB block pre-program and erase time 128 KB block pre-program and erase time Minimum operating frequency for program and erase operations 6 400 400 500 1250 -- Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values. Initial factory condition: 100 program/erase cycles, 25 oC, using a typical supply voltage measured at a minimum system frequency of 80 MHz. The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. Actual hardware programming times. This does not include software overhead. Page size is 256 bits (8 words). The read frequency of the flash can range up to the maximum operating frequency. There is no minimum read frequency condition. Table 15. Flash EEPROM Module Life (TA = TL to TH) Spec 1a 1b Characteristic Number of program/erase cycles per block for 16 KB, 48 KB, and 64 KB blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) Data retention Blocks with 0-1,000 P/E cycles Blocks with 1,001-100,000 P/E cycles Symbol P/E P/E Retention 20 5 -- -- years Min. 100,000 1000 Typical 1 -- 100,000 Unit cycles cycles 2 1 Typical endurance is evaluated at 25o C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 23 Electrical Characteristics Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 16. FLASH_BIU Settings vs. Frequency of Operation 1 Maximum Frequency (MHz) Up to and including 82 MHz 5 APC 0b001 RWSC 0b001 WWSC 0b01 DPFEN 2 0b00 0b01 0b11 0b00 0b01 0b11 0b00 0b01 0b11 0b00 IPFEN 2 0b00 0b01 0b11 0b00 0b01 0b11 0b00 0b01 0b11 0b00 PFLIM 3 0b000 to 0b110 0b000 to 0b110 0b000 to 0b110 0b000 BFEN 4 0b0 0b1 0b0 0b1 0b0 0b1 0b0 Up to and including 102 MHz 6 0b001 0b010 0b01 Up to and including 135 MHz 7 0b010 0b011 0b01 Default setting after reset 1 2 3 4 5 6 7 0b111 0b111 0b11 Illegal combinations exist. Use entries from the same row in this table. For maximum flash performance, set to 0b11. For maximum flash performance, set to 0b110. For maximum flash performance, set to 0b1. 82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM). 102 MHz parts allow for 100 MHz system clock + 2% FM. 135 MHz parts allow for 132 MHz system clock + 2% FM. 3.12 3.12.1 AC Specifications Pad AC Specifications Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V) 1 SRC / DSC (binary) 11 Out Delay 2, 3, 4 (ns) 26 82 75 137 377 476 16 43 34 61 192 239 Rise / Fall 4, 5 (ns) 15 60 40 80 200 260 8 30 15 35 100 125 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200 Spec Pad 1 Slow high voltage (SH) 01 00 11 2 Medium high voltage (MH) 01 00 MPC5565 Microcontroller Data Sheet, Rev. 2.0 24 Freescale Semiconductor Electrical Characteristics Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V) 1 (continued) Spec Pad SRC / DSC (binary) 00 3 Fast 01 10 11 4 5 1 2 3 4 5 Out Delay 2, 3, 4 (ns) Rise / Fall 4, 5 (ns) 2.7 Load Drive (pF) 10 20 30 50 50 50 3.1 2.5 2.4 2.3 Pullup/down (3.6 V max) Pullup/down (5.5 V max) -- -- -- -- 7500 9000 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: VDD = 1.35-1.65 V; VDDE = 1.62-1.98 V; VDDEH = 4.5-5.25 V; VDD33 and VDDSYN = 3.0-3.6 V; and TA = TL to TH. This parameter is supplied for reference and is guaranteed by design (not tested). The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. The output delay and rise and fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization rather than 100% tested. Table 18. Derated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V) 1 Spec Pad SRC/DSC (binary) 11 Out Delay 2, 3, 4 (ns) 39 120 101 188 507 597 23 64 50 90 261 305 Rise / Fall 3, 5 (ns) 23 87 52 111 248 312 12 44 22 50 123 156 2.4 3.2 2.2 2.1 2.1 -- -- 7500 9500 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200 10 20 30 50 50 50 1 Slow high voltage (SH) 01 00 11 2 Medium high voltage (MH) 01 00 00 3 Fast 01 10 11 4 5 1 Pullup/down (3.6 V max) Pullup/down (5.5 V max) -- -- These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: VDD = 1.35-1.65 V; VDDE = 3.0-3.6 V; VDDEH = 3.0-3.6 V; VDD33 and VDDSYN = 3.0-3.6 V; and TA = TL to TH. 2 This parameter is supplied for reference and guaranteed by design (not tested). MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 25 Electrical Characteristics 3 4 The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal. The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. 5 This parameter is guaranteed by characterization rather than 100% tested. VDD / 2 Pad internal data input signal Rising-edge out delay Falling-edge out delay VOH Pad output VOL Figure 4. Pad Output Delay 3.13 3.13.1 Spec 1 2 3 4 1 AC Timing Reset and Configuration Pin Timing Table 19. Reset and Configuration Pin Timing 1 Characteristic RESET pulse width RESET glitch detect pulse width PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid Symbol tRPW tGPW tRCSU tRCH Min. 10 2 10 0 Max. -- -- -- -- Unit tCYC tCYC tCYC tCYC Reset timing specified at: VDDEH = 3.0-5.25 V and TA = TL to TH. MPC5565 Microcontroller Data Sheet, Rev. 2.0 26 Freescale Semiconductor Electrical Characteristics 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG 4 Figure 5. Reset and Configuration Pin Timing 3.13.2 Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 IEEE 1149.1 Interface Timing Table 20. JTAG Pin AC Electrical Characteristics 1 Characteristic Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Min. 100 40 -- 5 25 -- 0 -- 100 40 -- -- -- 50 50 Max. -- 60 3 -- -- 20 -- 20 -- -- 50 50 50 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCK cycle time TCK clock pulse width (measured at VDDE / 2) TCK rise and fall times (40% to 70%) TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance JCOMP assertion time JCOMP setup time to TCK low TCK falling-edge to output valid TCK falling-edge to output valid out of high impedance TCK falling-edge to output high impedance (Hi-Z) Boundary scan input valid to TCK rising-edge TCK rising-edge to boundary scan input invalid These specifications apply to JTAG boundary scan only. JTAG timing specified at: VDDE = 3.0-3.6 V and TA = TL to TH. Refer to Table 21 for Nexus specifications. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 27 Electrical Characteristics TCK 2 3 2 1 3 Figure 6. JTAG Test Clock Input Timing TCK 4 5 TMS, TDI 6 7 8 TDO Figure 7. JTAG Test Access Port Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 28 Freescale Semiconductor Electrical Characteristics TCK 10 JCOMP 9 Figure 8. JTAG JCOMP Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 29 Electrical Characteristics TCK 11 13 Output signals 12 Output signals 14 15 Input signals Figure 9. JTAG Boundary Scan Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 30 Freescale Semiconductor Electrical Characteristics 3.13.3 Spec 1 2 3 4 5 6 7 8 9 10 11 Nexus Timing Table 21. Nexus Debug Port Timing 1 Characteristic Symbol tMCYC tMDC 3 3 3 Min. 12 40 -1.5 -1.5 -1.5 4.0 1 4 4 Max. 8 60 3.0 3.0 3.0 -- -- -- 60 -- -- Unit tCYC % ns ns ns tTCYC tMCYC tCYC % ns ns MCKO cycle time MCKO duty cycle MCKO low to MDO data valid tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV MCKO low to MSEO data valid MCKO low to EVTO data valid EVTI pulse width EVTO pulse width TCK cycle time TCK duty cycle TDI, TMS data setup time TDI, TMS data hold time TCK low to TDO data valid 40 8 5 12 VDDE = 2.25-3.0 V VDDE = 3.0-3.6 V RDY valid to MCKO 5 0 0 -- -- 12 10 -- ns ns -- 13 1 2 3 4 5 JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35-1.65 V, VDDE = 2.25-3.6 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The Nexus AUX port runs up to 82 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is greater than 82 MHz. MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs. Limit the maximum frequency to approximately 16 MHz (VDDE = 2.25-3.0 V) or 20 MHz (VDDE = 3.0-3.6 V) to meet the timing specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification. The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly. 1 2 MCKO 4 5 MDO MSEO EVTO 3 Output Data Valid Figure 10. Nexus Output Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 31 Electrical Characteristics TCK 10 11 TMS, TDI 12 TDO Figure 11. Nexus TDI, TMS, TDO Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 32 Freescale Semiconductor Electrical Characteristics 3.13.4 External Bus Interface (EBI) Timing Table 22 lists the timing information for the external bus interface (EBI). Table 22. Bus Operation Timing1 Characteristic and Description CLKOUT period CLKOUT duty cycle CLKOUT rise time CLKOUT fall time CLKOUT positive edge to output signal invalid or Hi-Z (hold time) External bus interface CS[0:3] ADDR[8:31] DATA[0:31] 5 BDIP OE RD_WR TA TEA 6 TS WE/BE[0:3] 7 CLKOUT positive edge to output signal invalid or Hi-Z (hold time) Calibration bus interface CAL_CS[0, 2:3] CAL_ADDR[10:30] CAL_DATA[0:15] CAL_OE CAL_RD_WR CAL_TS CAL_WE/BE[0:1] tCCOH 1.08 -- 1.5 1.5 1.08 -- 1.5 1.08 -- ns EBTS = 1 Hold time selectable via SIU_ECCR [EBTS] bit. External Bus Frequency 2, 3 Symbol Spec 40 MHz Min. Max. 56 MHz Min. Max. 66 MHz Min. Max. Unit Notes 1 2 3 4 TC tCDC tCRT tCFT tCOH 24.4 45% -- -- 1.08 -- 55% -- 4 17.5 45% -- -- 1.08 -- 55% -- 4 14.9 45% -- -- 1.08 -- 55% -- 4 ns TC ns ns Signals are measured at 50% VDDE. --4 -- --4 -- --4 -- EBTS = 0 ns EBTS = 1 Hold time selectable via SIU_ECCR [EBTS] bit. 1.5 1.5 1.5 5 EBTS = 0 MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 33 Electrical Characteristics Table 22. Bus Operation Timing1 (continued) Characteristic and Description CLKOUT positive edge to output signal valid (output delay) External bus interface CS[0:3] ADDR[8:31] DATA[0:31] 5 BDIP OE RD_WR TA TEA 6 TS WE/BE[0:3] 7 CLKOUT positive edge to output signal valid (output delay) Calibration bus interface CAL_CS[0, 2:3] CAL_ADDR[10:30] CAL_DATA[0:15] CAL_OE CAL_RD_WR CAL_TS CAL_WE/BE[0:1] Input signal valid to CLKOUT positive edge (setup time) External bus interface ADDR[8:31] DATA[0:31] 5 RD_WR TA TEA 6 TS Input signal valid to CLKOUT positive edge (setup time) Calibration bus interface CAL_ADDR[10:30] CAL_DATA[0:15] CAL_RD_WR CAL_TS tCCIS 11.0 -- 8.0 -- 6.0 -- ns tCCOV -- 12.0 11.08 -- 9.5 8.58 -- 8.0 EBTS = 1 Output valid time selectable via SIU_ECCR [EBTS] bit. 7.08 ns External Bus Frequency 2, 3 Symbol Spec 40 MHz Min. Max. 56 MHz Min. Max. 66 MHz Min. Max. Unit Notes tCOV -- 10.08 -- 11.0 7.58 -- 8.5 6.08 ns 7.0 EBTS = 0 EBTS = 1 Output valid time selectable via SIU_ECCR [EBTS] bit. 6 EBTS = 0 6a 7 tCIS 10.0 -- 7.0 -- 5.0 -- ns MPC5565 Microcontroller Data Sheet, Rev. 2.0 34 Freescale Semiconductor Electrical Characteristics Table 22. Bus Operation Timing1 (continued) Characteristic and Description CLKOUT positive edge to input signal invalid (hold time) External bus interface ADDR[8:31] DATA[0:31] 5 RD_WR TA TEA 6 TS CLKOUT positive edge to input signal invalid (hold time) Calibration bus interface CAL_ADDR[10:30] CAL_DATA[0:15] CAL_RD_WR CAL_TS 1 2 External Bus Frequency 2, 3 Symbol Spec 40 MHz Min. Max. 56 MHz Min. Max. 66 MHz Min. Max. Unit Notes 8 tCIH 1.0 -- 1.0 -- 1.0 -- ns tCCIH 1.0 -- 1.0 -- 1.0 -- ns 3 4 5 6 7 8 EBI timing specified at: VDDE = 1.6-3.6 V (unless stated otherwise); TA = TL to TH; and CL = 30 pF with DSC = 0b10. Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM. The external bus is limited to half the speed of the internal bus. Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V). Due to pin limitations, the DATA[16:31] signals are not available on the 324 package. Due to pin limitations, the TEA signal is not available on the 324 package. Due to pin limitations, the WE/BE[2:3] signals are not available on the 324 package. SIU_ECCR[EBTS] = 0 timings are tested and valid at VDDE = 2.25-3.6 V only; SIU_ECCR[EBTS] = 1 timings are tested and valid at VDDE = 1.6-3.6 V. Voh_f VDDE / 2 CLKOUT Vol_f 3 2 2 4 1 Figure 12. CLKOUT Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 35 Electrical Characteristics CLKOUT VDDE / 2 6 5 5 VDDE / 2 Output bus VDDE / 2 6 5 5 Output signal VDDE / 2 6 Output signal VDDE / 2 Figure 13. Synchronous Output Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 36 Freescale Semiconductor Electrical Characteristics CLKOUT VDDE / 2 7 8 Input bus VDDE / 2 7 8 Input signal VDDE / 2 Figure 14. Synchronous Input Timing 3.13.5 Spec 1 2 3 1 2 External Interrupt Timing (IRQ Signals) Table 23. External Interrupt Timing 1 Characteristic Symbol tIPWL TIPWH tICYC Min. 3 3 6 Max. -- -- -- Unit tCYC tCYC tCYC IRQ pulse-width low IRQ pulse-width high IRQ edge-to-edge time 2 IRQ timing specified at: VDDEH = 3.0-5.25 V and TA = TL to TH. Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both. MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 37 Electrical Characteristics IRQ 1 3 2 Figure 15. External Interrupt Timing 3.13.6 Spec 1 2 1 2 eTPU Timing Table 24. eTPU Timing 1 Characteristic Symbol tICPW tOCPW Min. 4 2 2 Max -- -- Unit tCYC tCYC eTPU input channel pulse width eTPU output channel pulse width eTPU timing specified at: VDDEH = 3.0-5.25 V and TA = TL to TH. This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). 2 eTPU output eTPU input and TCRCLK 1 Figure 16. eTPU Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 38 Freescale Semiconductor Electrical Characteristics 3.13.7 Spec 1 2 1 2 eMIOS Timing Table 25. eMIOS Timing 1 Characteristic eMIOS input pulse width eMIOS output pulse width Symbol tMIPW tMOPW Min. 4 1 2 Max. -- -- Unit tCYC tCYC eMIOS timing specified at: VDDEH = 3.0-5.25 V and TA = TL to TH. This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR). 2 eMIOS output eMIOS input 1 Figure 17. eMIOS Timing 3.13.8 DSPI Timing Table 26. DSPI Timing1' 2 80 MHz 112 MHz Min. Max. 132 MHz Unit Min. Max. Spec Characteristic SCK cycle time3, 4 PCS to SCK After SCK delay5 delay6 Symbol Min. Max. 1 2 3 4 5 6 7 8 tSCK tCSC tASC tSDC tA tDIS tPCSC tPASC 24.4 ns 23 22 (tSCK / 2) - 2 ns 2.9 ms -- -- (tSCK / 2) + 2 ns 17.5 ns 15 14 2.1 ms -- -- 14.8 ns 13 12 1.8 ms -- -- -- ns ns ns ns ns ns ns SCK duty cycle Slave access time (SS active to SOUT driven) Slave SOUT disable time (SS inactive to SOUT Hi-Z, or invalid) PCSx to PCSS time PCSS to PCSx time (tSCK / 2) (tSCK / 2) (tSCK / 2) (tSCK / 2) - 2 ns + 2 ns - 2 ns + 2 ns -- -- 4 5 25 25 -- -- -- -- 4 5 25 25 -- -- -- -- 4 5 25 25 -- -- MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 39 Electrical Characteristics Table 26. DSPI Timing1' 2 (continued) 80 MHz Spec 112 MHz Min. Max. 132 MHz Unit Min. Max. Characteristic Data setup time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) Data hold time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) Data valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Symbol Min. Max. tSUI 20 2 -4 20 tHI -4 7 21 -4 tSUO -- -- -- -- tHO -5 5.5 8 -5 -- -- -- -- -5 5.5 4 -5 -- -- -- -- -5 5.5 3 -5 -- -- -- -- ns ns ns ns 5 25 18 5 -- -- -- -- 5 25 14 5 -- -- -- -- 5 25 13 5 ns ns ns ns -- -- -- -- -4 7 14 -4 -- -- -- -- -4 7 12 -4 -- -- -- -- ns ns ns ns -- -- -- -- 20 2 3 20 -- -- -- -- 20 2 6 20 -- -- -- -- ns ns ns ns 9 10 11 12 1 2 3 4 5 6 7 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: VDDEH = 3.0-5.25 V;TA = TL to TH; and CL = 50 pF with SRC = 0b11. Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM. The minimum SCK cycle time restricts the baud rate selection for the given system clock rate. These numbers are calculated based on two MPC55xx devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10. MPC5565 Microcontroller Data Sheet, Rev. 2.0 40 Freescale Semiconductor Electrical Characteristics 2 PCSx 4 SCK output (CPOL=0) 4 1 3 SCK output (CPOL=1) 9 SIN 10 Data 12 SOUT First data Data Last data 11 Last data First data Figure 18. DSPI Classic SPI Timing--Master, CPHA = 0 PCSx SCK output (CPOL=0) 10 SCK output (CPOL=1) 9 SIN First data 12 SOUT First data Data Data Last data 11 Last data Figure 19. DSPI Classic SPI Timing--Master, CPHA = 1 MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 41 Electrical Characteristics 2 SS 1 SCK input (CPOL=0) 4 SCK input (CPOL=1) 5 SOUT First data 9 SIN 10 Data 12 Data 11 4 3 6 Last data First data Last data Figure 20. DSPI Classic SPI Timing--Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) 5 SOUT 11 12 First data 9 10 Data Last data Data Last data 6 SIN First data Figure 21. DSPI Classic SPI Timing--Slave, CPHA = 1 MPC5565 Microcontroller Data Sheet, Rev. 2.0 42 Freescale Semiconductor Electrical Characteristics 3 PCSx 4 2 SCK output (CPOL=0) SCK output (CPOL=1) 9 SIN First data 12 SOUT First data Data Data 11 Last data Last data 4 1 10 Figure 22. DSPI Modified Transfer Format Timing--Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) 9 SIN First data Data 12 SOUT First data Data 10 Last data 11 Last data Figure 23. DSPI Modified Transfer Format Timing--Master, CPHA = 1 MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 43 Electrical Characteristics SS 2 1 3 SCK input (CPOL=0) 4 SCK input (CPOL=1) 5 SOUT First data 9 SIN First data Data Data 11 12 Last data 10 Last data 6 4 Figure 24. DSPI Modified Transfer Format Timing--Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) 5 SOUT 11 12 First data 9 10 Data Last data Data Last data 6 SIN First data Figure 25. DSPI Modified Transfer Format Timing--Slave, CPHA = 1 7 PCSS PCSx 8 Figure 26. DSPI PCS Strobe (PCSS) Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 44 Freescale Semiconductor Electrical Characteristics 3.13.9 Spec 2 3 4 5 6 7 8 1 eQADC SSI Timing Table 27. EQADC SSI Timing Characteristics Rating FCK period (tFCK = 1 / fFCK) 1, 2 Clock (FCK) high time Clock (FCK) low time SDS lead / lag time SDO lead / lag time EQADC data setup time (inputs) EQADC data hold time (inputs) Symbol tFCK tFCKHT tFCKLT tSDS_LL tSDO_LL tEQ_SU tEQ_HO Minimum 2 tSYS_CLK - 6.5 tSYS_CLK - 6.5 -7.5 -7.5 22 1 Typical -- -- -- -- -- -- -- Maximum 17 9 x (tSYS_CLK + 6.5) 8 x (tSYS_CLK + 6.5) +7.5 +7.5 -- -- Unit tSYS_CLK ns ns ns ns ns ns SS timing specified at VDDEH = 3.0-5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number. 2 3 FCK 5 SDS 25th 1st (MSB) 2nd 26th 4 4 6 SDO External device data sample at FCK falling-edge 8 7 SDI EQADC data sample at FCK rising-edge 1st (MSB) 2nd 5 25th 26th Figure 27. EQADC SSI Timing MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 45 Mechanicals 4 4.1 Mechanicals MPC5565 324 PBGA Pinouts NOTE The MPC5500 devices are pin compatible for software portability and use the primary function names to label the pins in the BGA diagram. Although some devices do not support all the primary functions shown in the BGA diagram, the muxed and GPIO signals on those pins remain available. See the signals chapter in the device reference manual for the signal muxing. 1 2 VDD VSS 3 VSTBY VDD VSS 4 AN37 AN36 VDD VSS 5 AN11 AN39 AN8 VDD 6 7 8 AN1 AN0 AN21 AN10 9 AN5 AN4 AN3 AN18 10 VRH REF BYPC AN7 AN2 11 VRL AN23 AN22 AN6 12 AN27 AN26 AN25 AN24 13 AN28 AN31 AN30 AN29 14 AN35 AN32 AN33 15 VSSA0 VSSA0 VDDA0 16 AN12 AN13 AN14 17 18 19 20 VDD MDO0 VSS VDDE7 TMS 21 VDD33 VSS VDDE7 TCK TDO EVTI 22 VSS A Figure 28 is a pinout for the MPC5565 324 PBGA package. A VSS VDDA1 VSSA1 AN19 AN17 AN38 AN16 AN20 AN9 MDO11 MDO10 MDO8 MDO9 MDO5 MDO6 MDO7 MDO2 MDO3 MDO4 MDO1 VSS VDDE7 B VDD33 VDDE7 B VDD TDI TEST C D E ETPUA ETPUA C 30 31 ETPUA ETPUA ETPUA D 28 29 26 AN34 VDDEH AN15 9 ETPUA ETPUA ETPUA ETPUA E 24 27 25 21 F G H ETPUA ETPUA ETPUA ETPUA 23 22 17 18 ETPUA ETPUA ETPUA ETPUA 20 19 14 13 ETPUA ETPUA ETPUA VDDEH 16 15 10 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDE7 VSS VSS VSS VSS VSS VDDE7 JCOMP RDY EVTO F MCKO MSEO0 MSEO1 G GPIO 204 SINB H VDDEH GPIO 10 203 ETPUA ETPUA ETPUA ETPUA J 6 9 12 11 ETPUA ETPUA ETPUA ETPUA K 5 8 7 2 ETPUA ETPUA ETPUA ETPUA L 4 3 1 0 M N TCRCLK BDIP A CS3 CS2 CS1 WE1 CS0 WE0 SOUTB PCSB3 PCSB0 PCSB1 J PCSA3 PCSB4 SCKB PCSB2 K PCSB5 SOUTA SINA SCKA L VPP M VDDE2 VDDE2 VSS VSS VSS VSS PCSA1 PCSA0 PCSA2 PCSA4 TXDA PCSA5 VFLASH N CNTXC RXDA RSTOUT WKP CFG RXDB RST CFG P ADDR P 16 ADDR R 18 ADDR T 20 U V ADDR 22 ADDR 24 ADDR RD_WR VDD33 17 ADDR VDDE2 19 ADDR 21 ADDR 23 ADDR 25 ADDR 12 ADDR 13 ADDR 15 TA TS ADDR 14 ADDR 31 VSS VDD VDDE2 DATA 0 4 VDD VDDE2 DATA 1 DATA 2 5 VDDE2 VDD33 VDDE2 DATA 8 VDDE2 DATA 3 6 DATA 9 GPIO 206 DATA 4 7 DATA 10 DATA 5 DATA 6 8 CNRXC TXDB RESET R BOOT CFG1 PLL CFG2 Note: NC No connect. Reserved (W18 & Y19 are shorted to each other) VSS SYN T VDDEH PLL 6 CFG1 VDD VRC CTL VDD VSS BOOT CFG0 PLL CFG0 VRC33 VDD EXTAL U XTAL VDD SYN V W ADDR ADDR W VDDE2 30 26 ADDR Y 28 ADDR AA 29 AB VSS 1 ADDR 27 VSS VDD 2 VSS VDD VDDE2 3 DATA 11 GPIO 207 DATA 7 OE 9 DATA 12 DATA 13 DATA 14 DATA 15 EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 21 8 2 4 12 NC VSS NC EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 6 10 15 17 22 VDD33 Y VDD VSS 22 AA AB VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 3 5 9 13 23 16 19 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 20 0 1 4 7 11 14 18 10 11 12 13 14 15 16 17 18 19 20 ENG CLK 21 Figure 28. MPC5565 324 Package MPC5565 Microcontroller Data Sheet, Rev. 2.0 46 Freescale Semiconductor Mechanicals 4.2 MPC5565 324-Pin Package Dimensions The package drawings of the MPC5565 324-pin TEPBGA package are shown in Figure 29. Figure 29. MPC5565 324 TEPBGA Package MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 47 Mechanicals Figure 29. MPC5565 324 TEPBGA Package (continued) MPC5565 Microcontroller Data Sheet, Rev. 2.0 48 Freescale Semiconductor Revision History for the MPC5565 Data Sheet 5 Revision History for the MPC5565 Data Sheet The history of revisions made to this data sheet are shown in this section. The changes are divided into each revision of this document. The substantive changes incorporated in MPC5565 Data Sheet Rev. 1.0 to produce Rev. 2.0 of this document are grouped as follows: * Global and text changes * Table and figure changes Within each group, the changes are listed in sequential order. 5.1 Changes to Revision 1.0 in Revision 2.0 Table 28. Text Changes Between Rev. 1.0 and 2.0 The following table lists the substantive text changes made to paragraphs. Location Throughout: Changed `TA = TL - TH' to `TA = TL to TH.' Title page: Description of Changes Changed the Revision number from 1.0 to 2.0. Made the same changes in the lower left corner of the back page. Section 1, "Overview" * Fourth paragraph, First sentence: Deleted `of the MPC5500 family'; Second to last sentence: Deleted `can'. * Fifth paragraph, First sentence: Replaced `MPC5500 family' with `MPC5565'; Last sentence: Replaced `can be' with `is'. * Sixth paragraph, First sentence: Replaced `MPC5500 family' with `MPC5565'; * Second to last paragraph: Rewrote to read: The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC) The 324 package has 40-channels. Section 3.1, "Maximum Ratings: Changed title from `Maximum Rating' to `Maximum Ratings.' Section 3.2.1, "General Notes for Specifications at Maximum Junction Temperature" Updated the address of Semiconductor Equipment and Materials International 3081 Zanker Rd. San Jose, CA., 95134 (408) 943-6900 Section 3.7, "Power-Up/Down Sequencing" Last paragraph: Changed the first sentence FROM , , , the voltage on the pins goes to high-impedance until . . . TO. . .the pins go to a high-impedance state until . . . Section 3.7.3, "Power-Down Sequence (VRC33 Grounded)" Last sentence: Changed from: `This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset properly.' To: `This ensures that the digital 1.5 V logic, which is reset only by an ORed POR and can cause the 1.5 V supply to decrease less than its specification, resets correctly.' MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 49 Revision History for the MPC5565 Data Sheet Table 28. Text Changes Between Rev. 1.0 and 2.0 (continued) Location Section 4.1, "MPC5565 324 PBGA Pinouts" Added the following NOTE before the 324 BGA Map: NOTE The MPC5500 devices are pin compatible for software portability and use the primary function names to label the pins in the BGA diagram. Although some devices do not support all the primary functions shown in the BGA diagram, the muxed and GPIO signals on those pins remain available. See the signals chapter in the device reference manual for the signal muxing. Description of Changes The following table lists the information that changed in the tables between Rev. 1.0 and 2.0. Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0 Location Table 2 Absolute Maximum Ratings: * Added footnote 7 to Spec 12 `Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.' Table 4 EMI Testing Specifications: * Table Title: Footnote 1: Deleted the last sentence: "The values in this specification reflect EMI performance with frequency modulation (FM) turned off. For better EMI performance, enable FM.' Table 5 ESD Ratings: Changed footnote 2 from: * `Device failure is defined as: `If after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing will be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.' to: * Device failure is defined as: `If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature. Table 6 VCR/POR Electrical Specifications: * Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts. * Reformatted columns. Table 9 DC Electrical Specifications: * Added (TA = TL to TH) to the table title. * Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25-3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and VDDE3 have a range of 1.6-3.6 V if SIU_ECCR[EBTS] =1. Description of Changes MPC5565 Microcontroller Data Sheet, Rev. 2.0 50 Freescale Semiconductor Revision History for the MPC5565 Data Sheet Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0 (continued) Location Table 17 Pad AC Specifications: * Footnote 1, Changed `VDDEH = 4.5-5.5;' to `VDDEH = 4.5-5.25;' * Footnote 3, Changed from `Out delay. . .' to `The output delay. . .', * Changed from ` Add a maximum of one system clock to the output delay to get the output delay with respect to the system clock` to `To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay.' * Footnote 4: Changed `Delay' to `The output delay.' Table 19 Reset and Configuration Pin Timing * Footnote 1: Removed VDD =1.35-1.65. Table 20 JTAG Pin AC Electrical Characteristics * Footnote 1: Removed VDD =1.35-1.65; and VDD33 and VDDSYN = 3.0-3.6 V. Table 22 Bus Operation Timing: * Specifications 5 and 6. Changed EBTS to SIU_ECCR[EBTS]. * Specifications 7 and 8: Removed CS[0:3], BDIP, OE, and WE/BE[0:3] because these pins are not used on the input signal to CLKOUT. * Specification 7: Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on the input signal to CLKOUT. * Specification 8: Added to the beginning of the calibration section: CLKOUT positive edge to input signal invalid (hold time). Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on the input signal to CLKOUT. * Footnote 1: Deleted VDD = 1.35-1.65; and VDD33 and VDDSYN = 3.0-3.6 V. * Added footnote 2: "Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM.' * Added footnotes 5, 6, and 7, one each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin limitations, the DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package. * Footnote 8: Changed EBTS to SIU_ECCR[EBTS]. Table 23 External Interrupt Timing (IRQ Signals) * Footnote 1: Removed VDD = 1.35-1.65 V; changed VDDEH = 3.0-5.5 V to VDDEH = 3.0-5.25 V. Table 24 eTPU Timing * Footnote 1: Changed VDDEH = 3.0-5.5 V to VDDEH = 3.0-5.25 V. Table 25 eMIOS Timing * Footnote 1: Changed VDDEH = 3.0-5.5 V to VDDEH = 3.0-5.25 V. Table 26 DSPI Timing: * Specification 1: SCK cycle time. Changed 80 MHz column, Min.: from 25 to 24.4; 112 MHz columns, Min.: from 17.9 to 17.5, Max: from 2.0 to 2.1; 132 MHz columns, Min.: from 15.2 to 14.8, Max: from 1.7 to 1.8. * Footnote 1, changed `VDDEH = 3.0-5.5 V;' to `VDDEH = 3.0-5.25 V;' * Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, 135 MHz parts allow for 132 MHz system clock + 2% FM. Table 27 EQADC SSI Timing Characteristics * Footnote 1: Changed VDDEH = 3.0-5.5 V to VDDEH = 3.0-5.25 V. Description of Changes MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 51 Revision History for the MPC5565 Data Sheet 5.2 Changes to Revision 0.0 in Revision 1.0 Table 30. MPC5565 Changes Between Rev. 0.0 and 1.0 The following table lists the information that changed in the tables between Rev. 0.0 and 1.0. Location Table 6 VCR/POR Electrical Specifications: Description of Changes * Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5 negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts. Table 9 DC Electrical Specifications: * Added (TA = TL to TH) to the table title. Table 22 Bus Operation Timing: * External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts allow for 132 MHz system clock + 2% FM. * Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification. * Specs 7 and 8: Removed from external bus interface: BDIP, OE, and WE/BE[0:3]. * Footnote 1: Removed VDD = 1.35-1.65 V, and VDD33 and VDDSYN = 3.0-3.6 V. Table 25 eMIOS Timing: * Deleted (MTS) from the heading, table, and footnotes. * Footnote 1: Deleted `. . .fSYS = 132 MHz. . .', `. . .VDD33 and VDDSYN = 3.0-3.6 V. . .' and ` . . .and CL = 200 pF with SRC = 0b11.' * Added Footnote 2: `This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).' MPC5565 Microcontroller Data Sheet, Rev. 2.0 52 Freescale Semiconductor Revision History for the MPC5565 Data Sheet MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 53 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MPC5565 Rev. 2.0 11/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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